C8051F040/1/2/3/4/5/6/7
P0
P1
P2
P3
Crossbar Register Bits
PIN I/O 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
TX0
z
RX0
z
UART0EN: XBR0.2
SCK
zz
MISO
MOSI
zz
zz
SPI0EN: XBR0.1
NSS
z
z
SDA
z zzz
zz
SCL
z zz
zz
z
SMB0EN: XBR0.0
TX1
z zzz
RX1
z zz
zz
zz
zz
zzz
UART1EN: XBR2.2
CEX0
z
zzz
zz
zzzz
CEX1
z zz
zz
zzzzz
CEX2
CEX3
zz
z
zz
zz
zzzzzz
zzzzzzz
PCA0ME: XBR0.[5:3]
CEX4
z
z
zzzzzzzz
CEX5
z
zzzzzzzzz
ECI
zzzzz
zz
zzzzzzzzzz
ECI0E: XBR0.6
CP0
zzzzz
zz
zzzzzzzzzzz
CP0E: XBR0.7
CP1
zzzzz
zz
zzzzzzzzzzzz
CP1E: XBR1.0
CP2
zzzzz
zz
zzzzzzzzzzzzz
CP2E: XBR3.2
T0
zzzzz
zz
zzzzzzzzzzzzzz
T0E: XBR1.1
/INT0
zzzzz
zz
zzzzzzzzzzzzzzz
INT0E: XBR1.2
T1
zzzzz
zz
zzzzzzzzzzzzzzzz
T1E: XBR1.3
/INT1
zzzzz
zz
zzzzzzzzzzzzzzzzz
INT1E: XBR1.4
T2
zzzzz
zz
zzzzzzzzzzzzzzzzzz
T2E: XBR1.5
T2EX
zzzzz
zz
zzzzzzzzzzzzzzzzzzz
T2EXE: XBR1.6
T3
zzzzz
zz
zzzzzzzzzzzzzzzzzzz
T3E: XBR3.0
T3EX
zzzzz
zz
zzzzzzzzzzzzzzzzzzz
T3EXE: XBR3.1
T4
zzzzz
zz
zzzzzzzzzzzzzzzzzzz
T4E: XBR2.3
T4EX
zzzzz
zz
zzzzzzzzzzzzzzzzzzz
T4EXE: XBR2.4
/SYSCLK z z z z z
zz
z z z z z z z z z z z z z z z z z z z SYSCKE: XBR1.7
CNVSTR0 z z z z z
zz
z z z z z z z z z z z z z z z z z z z CNVSTE0: XBR2.0
CNVSTR2 z z z z z
zz
z z z z z z z z z z z z z z z z z z z CNVSTE2: XBR3.2
AIN1 Inputs/Non-muxed Addr H Muxed Addr H/Non-muxed Addr L Muxed Data/Non-muxed Data
Figure 17.6. Crossbar Example:
(EMIFLE = 1; EMIF in Multiplexed Mode; P1MDIN = 0xE3;
XBR0 = 0x05; XBR1 = 0x14; XBR2 = 0x42)
Rev. 1.5
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