C8051F045 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

SFR Definition 17.4. XBR3: Port I/O Crossbar Register 3

R/W

R

R

R

R/W

R/W

R/W

R/W

Reset Value

CTXOUT —

—

—

CP2E CNVST2E T3EXE

T3E 00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0xE4

SFR Page: F

Bit7:

Bit6-4:

Bit3:

Bit2:

Bit1:

Bit0:

CTXOUT: CAN Transmit Pin (CTX) Output Mode.

0: CTX pin output mode is configured as open-drain.

1: CTX pin output mode is configured as push-pull.

Reserved

CP2E: CP2 Output Enable Bit.

0: CP2 unavailable at Port pin.

1: CP2 routed to Port pin.

CNVST2E: ADC2 External Convert Start Input Enable Bit (C8051F040/1/2/3 only).

0: CNVST2 for ADC2 unavailable at Port pin.

1: CNVST2 for ADC2 routed to Port pin.

T3EXE: T3EX Input Enable Bit.

0: T3EX unavailable at Port pin.

1: T3EX routed to Port pin.

T3E: T3 Input Enable Bit.

0: T3 unavailable at Port pin.

1: T3 routed to Port pin.

SFR Definition 17.5. P0: Port0 Data

R/W

P0.7

Bit7

R/W

P0.6

Bit6

R/W

P0.5

Bit5

R/W

P0.4

Bit4

R/W

P0.3

Bit3

R/W

P0.2

Bit2

R/W

P0.1

Bit1

R/W

Reset Value

P0.0 11111111

Bit0

Bit

Addressable

SFR Address: 0x80

SFR Page: All Pages

Bits7-0:

P0.[7:0]: Port0 Output Latch Bits.

(Write - Output appears on I/O pins per XBR0, XBR1, XBR2, and XBR3 Registers)

0: Logic Low Output.

1: Logic High Output (open if corresponding P0MDOUT.n bit = 0).

(Read - Regardless of XBR0, XBR1, XBR2, and XBR3 Register settings).

0: P0.n pin is logic low.

1: P0.n pin is logic high.

Note: P0.7 (/WR), P0.6 (/RD), and P0.5 (ALE) can be driven by the External Data Memory

Interface. See Section “16. External Data Memory Interface and On-Chip XRAM” on

page 187 for more information. See also SFR Definition 17.3 for information about configur-

ing the Crossbar for External Memory accesses.

Rev. 1.5

215

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