C8051F045 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

19.3.2. Master Receiver Mode

Serial data is received on SDA while the serial clock is output on SCL. The SMBus0 interface generates a

START followed by the first data byte containing the address of the target slave and the data direction bit.

In this case the data direction bit (R/W) will be logic 1 to indicate a "READ" operation. The SMBus0 inter-

face receives serial data from the slave and generates the clock on SCL. After each byte is received,

SMBus0 generates an ACK or NACK depending on the state of the AA bit in register SMB0CN. SMBus0

generates a STOP condition to indicate the end of the serial transfer.

S

SLA

RA

Data Byte

A

Data Byte

NP

Interrupt

Interrupt

Interrupt

Interrupt

Received by SMBus

Interface

Transmitted by

SMBus Interface

S = START

P = STOP

A = ACK

N = NACK

R = READ

SLA = Slave Address

Figure 19.5. Typical Master Receiver Sequence

19.3.3. Slave Transmitter Mode

Serial data is transmitted on SDA while the serial clock is received on SCL. The SMBus0 interface receives

a START followed by data byte containing the slave address and direction bit. If the received slave address

matches the address held in register SMB0ADR, the SMBus0 interface generates an ACK. SMBus0 will

also ACK if the general call address (0x00) is received and the General Call Address Enable bit

(SMB0ADR.0) is set to logic 1. In this case the data direction bit (R/W) will be logic 1 to indicate a "READ"

operation. The SMBus0 interface receives the clock on SCL and transmits one or more bytes of serial

data, waiting for an ACK from the master after each byte. SMBus0 exits slave mode after receiving a

STOP condition from the master.

Interrupt

S

SLA

RA

Data Byte

A

Data Byte

NP

Interrupt

Interrupt

Interrupt

Received by SMBus

Interface

Transmitted by

SMBus Interface

S = START

P = STOP

N = NACK

W = WRITE

SLA = Slave Address

Figure 19.6. Typical Slave Transmitter Sequence

Rev. 1.5

243

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