C8051F045 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

19.3.4. Slave Receiver Mode

Serial data is received on SDA while the serial clock is received on SCL. The SMBus0 interface receives a

START followed by data byte containing the slave address and direction bit. If the received slave address

matches the address held in register SMB0ADR, the interface generates an ACK. SMBus0 will also ACK if

the general call address (0x00) is received and the General Call Address Enable bit (SMB0ADR.0) is set to

logic 1. In this case the data direction bit (R/W) will be logic 0 to indicate a "WRITE" operation. The

SMBus0 interface receives one or more bytes of serial data; after each byte is received, the interface

transmits an ACK or NACK depending on the state of the AA bit in SMB0CN. SMBus0 exits Slave Receiver

Mode after receiving a STOP condition from the master.

Interrupt

S

SLA

WA

Data Byte

A

Data Byte

AP

Interrupt

Received by SMBus

Interface

Transmitted by

SMBus Interface

Interrupt

Interrupt

S = START

P = STOP

A = ACK

R = READ

SLA = Slave Address

Figure 19.7. Typical Slave Receiver Sequence

244

Rev. 1.5

Share Link: