C8051F045 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

SFR Definition 21.3. SBUF0: UART0 Data Buffer

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0x99

SFR Page: 0

Bits7-0:

SBUF0.[7:0]: UART0 Buffer Bits 7-0 (MSB-LSB)

This is actually two registers; a transmit and a receive buffer register. When data is moved to

SBUF0, it goes to the transmit buffer and is held for serial transmission. Moving a byte to

SBUF0 is what initiates the transmission. When data is moved from SBUF0, it comes from

the receive buffer.

SFR Definition 21.4. SADDR0: UART0 Slave Address

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0xA9

SFR Page: 0

Bits7-0:

SADDR0.[7:0]: UART0 Slave Address

The contents of this register are used to define the UART0 slave address. Register SADEN0

is a bit mask to determine which bits of SADDR0 are checked against a received address:

corresponding bits set to logic 1 in SADEN0 are checked; corresponding bits set to logic 0

are “don’t cares”.

SFR Definition 21.5. SADEN0: UART0 Slave Address Enable

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0xB9

SFR Page: 0

Bits7-0:

SADEN0.[7:0]: UART0 Slave Address Enable

Bits in this register enable corresponding bits in register SADDR0 to determine the UART0

slave address.

0: Corresponding bit in SADDR0 is a “don’t care”.

1: Corresponding bit in SADDR0 is checked against a received address.

276

Rev. 1.5

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