C8051F045 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

24.3. Register Descriptions for PCA0

Following are detailed descriptions of the special function registers related to the operation of PCA0.

SFR Definition 24.1. PCA0CN: PCA Control

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

CF

CR

CCF5 CCF4 CCF3 CCF2 CCF1

CCF0 00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0xD8

SFR Page: 0

Bit7:

Bit6:

Bit5:

Bit4:

Bit3:

Bit2:

Bit1:

Bit0:

CF: PCA Counter/Timer Overflow Flag.

Set by hardware when the PCA0 Counter/Timer overflows from 0xFFFF to 0x0000. When

the Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the CPU to vec-

tor to the CF interrupt service routine. This bit is not automatically cleared by hardware and

must be cleared by software.

CR: PCA0 Counter/Timer Run Control.

This bit enables/disables the PCA0 Counter/Timer.

0: PCA0 Counter/Timer disabled.

1: PCA0 Counter/Timer enabled.

CCF5: PCA0 Module 5 Capture/Compare Flag.

This bit is set by hardware when a match or capture occurs. When the CCF interrupt is

enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This

bit is not automatically cleared by hardware and must be cleared by software.

CCF4: PCA0 Module 4 Capture/Compare Flag.

This bit is set by hardware when a match or capture occurs. When the CCF interrupt is

enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This

bit is not automatically cleared by hardware and must be cleared by software.

CCF3: PCA0 Module 3 Capture/Compare Flag.

This bit is set by hardware when a match or capture occurs. When the CCF interrupt is

enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This

bit is not automatically cleared by hardware and must be cleared by software.

CCF2: PCA0 Module 2 Capture/Compare Flag.

This bit is set by hardware when a match or capture occurs. When the CCF interrupt is

enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This

bit is not automatically cleared by hardware and must be cleared by software.

CCF1: PCA0 Module 1 Capture/Compare Flag.

This bit is set by hardware when a match or capture occurs. When the CCF interrupt is

enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This

bit is not automatically cleared by hardware and must be cleared by software.

CCF0: PCA0 Module 0 Capture/Compare Flag.

This bit is set by hardware when a match or capture occurs. When the CCF interrupt is

enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This

bit is not automatically cleared by hardware and must be cleared by software.

312

Rev. 1.5

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