C8051F045 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

25. JTAG (IEEE 1149.1)

Each MCU has an on-chip JTAG interface and logic to support boundary scan for production and in-sys-

tem testing, Flash read/write operations, and non-intrusive in-circuit debug. The JTAG interface is fully

compliant with the IEEE 1149.1 specification. Refer to this specification for detailed descriptions of the Test

Interface and Boundary-Scan Architecture. Access of the JTAG Instruction Register (IR) and Data Regis-

ters (DR) are as described in the Test Access Port and Operation of the IEEE 1149.1 specification.

The JTAG interface is accessed via four dedicated pins on the MCU: TCK, TMS, TDI, and TDO.

Through the 16-bit JTAG Instruction Register (IR), any of the seven instructions shown in Figure 25.1 can

be commanded. There are three DRs associated with JTAG Boundary-Scan, and four associated with

Flash read/write operations on the MCU.

JTAG Register Definition 25.1. IR: JTAG Instruction Register

Bit15

Reset Value

0x0000

Bit0

IR

Value

0x0000

0x0002

0x0004

0xFFFF

0x0082

0x0083

0x0084

Instruction

Description

EXTEST Selects the Boundary Data Register for control and observability of all

device pins

SAMPLE/ Selects the Boundary Data Register for observability and presetting the

PRELOAD scan-path latches

IDCODE Selects device ID Register (DEVICEID)

BYPASS Selects Bypass Data Register

Flash Control Selects FLASHCON Register to control how the interface logic responds

to reads and writes to the FLASHDAT Register

Flash Data Selects FLASHDAT Register for reads and writes to the Flash memory

Flash Address Selects FLASHADR Register which holds the address of all Flash read,

write, and erase operations

Rev. 1.5

317

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