C8051F045 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

SFR Definition 7.3. ADC2CF: ADC2 Configuration

R/W

AD2SC4

Bit7

R/W

AD2SC3

Bit6

R/W

AD2SC2

Bit5

R/W

AD2SC1

Bit4

R/W

AD2SC0

Bit3

R

R/W

R/W

Reset Value

- AMP2GN1 AMP2GN0 11111000

Bit2

Bit1

Bit0

SFR Address: 0xBC

SFR Page: 2

Bits7-3:

AD2SC4-0: ADC2 SAR Conversion Clock Period Bits

SAR Conversion clock is derived from system clock by the following equation, where

AD2SC refers to the 5-bit value held in AD2SC4-0. SAR conversion clock requirements are

given in Table 7.2.

AD2SC  -S---Y----S---C-----L---K--- – 1 *

CLKSAR2

or

CLKSAR2

=

----S---Y----S---C----L----K------ –

AD2SC + 1

*Note: AD2SC is the rounded-up result.

Bit2:

Bits1-0:

UNUSED. Read = 0b. Write = don’t care.

AMP2GN1-0: ADC2 Internal Amplifier Gain (PGA)

00: Gain = 0.5

01: Gain = 1

10: Gain = 2

11: Gain = 4

Rev. 1.5

97

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