C8051F045 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

SFR Definition 7.4. ADC2CN: ADC2 Control

R/W

AD2EN

Bit7

R/W

AD2TM

Bit6

R/W

R/W

R/W

R/W

AD2INT AD2BUSY AD2CM2 AD2CM1

Bit5

Bit4

Bit3

Bit2

R/W

AD2CM0

Bit1

R/W

Reset Value

AD2WINT 00000000

Bit0

SFR Address: 0xE8

SFR Page: 2

Bit7:

AD2EN: ADC2 Enable Bit.

0: ADC2 Disabled. ADC2 is in low-power shutdown.

1: ADC2 Enabled. ADC2 is active and ready for data conversions.

Bit6:

AD2TM: ADC2 Track Mode Bit.

0: Normal Track Mode: When ADC2 is enabled, tracking is continuous unless a conversion is in

process.

1: Low-power Track Mode: Tracking defined by AD2CM2-0 bits (see below).

Bit5:

AD2INT: ADC2 Conversion Complete Interrupt Flag.

This flag must be cleared by software.

0: ADC2 has not completed a data conversion since the last time this flag was cleared.

1: ADC2 has completed a data conversion.

Bit4:

AD2BUSY: ADC2 Busy Bit.

Read:

0: ADC2 Conversion is complete or a conversion is not currently in progress. AD2INT is set to

logic 1 on the falling edge of AD2BUSY.

1: ADC2 Conversion is in progress.

Write:

0: No Effect.

1: Initiates ADC2 Conversion if AD2CM2-0 = 000b

Bits3-1: AD2CM2-0: ADC2 Start of Conversion Mode Select.

AD2TM = 0:

000: ADC2 conversion initiated on every write of ‘1’ to AD2BUSY.

001: ADC2 conversion initiated on overflow of Timer 3.

010: ADC2 conversion initiated on rising edge of external CNVSTR2 or CNVSTR0.

011: ADC2 conversion initiated on overflow of Timer 2.

1xx: ADC2 conversion initiated on write of ‘1’ to AD0BUSY (synchronized with ADC0 software-

commanded conversions).

AD2TM = 1:

000: Tracking initiated on write of ‘1’ to AD2BUSY and lasts 3 SAR2 clocks, followed by conver-

sion.

001: Tracking initiated on overflow of Timer 3 and lasts 3 SAR2 clocks, followed by conversion.

010: ADC2 tracks only when CNVSTR2 (or CNVSTR0, See Section 7.2.1) input is logic low; con-

version starts on rising CNVSTR2 edge.

011: Tracking initiated on overflow of Timer 2 and lasts 3 SAR2 clocks, followed by conversion.

1xx: Tracking initiated on write of ‘1’ to AD0BUSY and lasts 3 SAR2 clocks, followed by conver-

sion.

Bit0:

AD2WINT: ADC2 Window Compare Interrupt Flag.

0: ADC2 window comparison data match has not occurred since this flag was last cleared.

1: ADC2 window comparison data match has occurred. This flag must be cleared in software.

An important note about external convert start (CNVSTR0 and CNVSTR2): If CNVSTR2 is enabled in

the digital crossbar (Section “17.1. Ports 0 through 3 and the Priority Crossbar Decoder”

on page 204), CNVSTR2 will be the external convert start signal for ADC2. However, if only

CNVSTR0 is enabled in the digital crossbar and CNVSTR2 is not enabled, then CNVSTR0 may

serve as the start of conversion for both ADC0 and ADC2.

98

Rev. 1.5

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