C8051F304 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F304

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F300/1/2/3/4/5

12.1. Priority Crossbar Decoder

The Priority Crossbar Decoder (Figure 12.3) assigns a priority to each I/O function, starting at the top with

UART0. When a digital resource is selected, the least significant unassigned Port pin is assigned to that

resource (excluding UART0, which is always at pins 4 and 5). If a Port pin is assigned, the Crossbar skips

that pin when assigning the next selected resource. Additionally, the Crossbar will skip Port pins whose

associated bits in the XBR0 register are set. The XBR0 register allows software to skip Port pins that are to

be used for analog input or GPIO.

Important Note on Crossbar Configuration: If a Port pin is claimed by a peripheral without use of the

Crossbar, its corresponding XBR0 bit should be set. This applies to P0.0 if VREF is enabled, P0.3 and/or

P0.2 if the external oscillator circuit is enabled, P0.6 if the ADC is configured to use the external conversion

start signal (CNVSTR), and any selected ADC or Comparator inputs. The Crossbar skips selected pins as

if they were already assigned, and moves to the next unassigned pin. Figure 12.3 shows the Crossbar

Decoder priority with no Port pins skipped (XBR0 = 0x00); Figure 12.4 shows the Crossbar Decoder prior-

ity with pins 6 and 2 skipped (XBR0 = 0x44).

SF Signals VREF

PIN I/O

01

TX0

RX0

SDA

SCL

CP0

CP0A

SYSCLK

CEX0

CEX1

CEX2

ECI

T0

T1

00

P0

x1 x2

234

CNVSTR

567

000000

XBR0[0:7]

Port pin potentially available to peripheral

SF Signals Special Function Signals are not assigned by the crossbar.

When these signals are enabled, the CrossBar must be

manually configured to skip their corresponding port pins.

Note: x1 refers to the XTAL1 signal; x2 refers to the XTAL2

signal.

Figure 12.3. Crossbar Priority Decoder with XBR0 = 0x00

104

Rev. 2.9

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