C8051F304 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F304

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F300/1/2/3/4/5

SF Signals VREF

PIN I/O

01

TX0

RX0

SDA

SCL

CP0

CP0A

SYSCLK

CEX0

CEX1

CEX2

ECI

T0

T1

00

P0

x1 x2

234

CNVSTR

567

100010

XBR0[0:7]

Port pin potentially available to peripheral

SF Signals

Port pin skipped by CrossBar

Special Function Signals are not assigned by the crossbar. When

these signals are enabled, the CrossBar must be manually

configured to skip their corresponding port pins. Note: x1 refers to

the XTAL1 signal; x2 refers to the XTAL2 signal.

Figure 12.4. Crossbar Priority Decoder with XBR0 = 0x44

Registers XBR1 and XBR2 are used to assign the digital I/O resources to the physical I/O Port pins. Note

that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus (SDA and

SCL). Either or both of the UART signals may be selected by the Crossbar. UART0 pin assignments are

fixed for bootloading purposes: when UART TX0 is selected, it is always assigned to P0.4; when UART

RX0 is selected, it is always assigned to P0.5. Standard Port I/Os appear contiguously after the prioritized

functions have been assigned. For example, if assigned functions that take the first 3 Port I/O (P0.[2:0]), 5

Port I/O are left for analog or GPIO use.

Rev. 2.9

105

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