C8051F342 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F342

Full Speed USB Flash MCU Family

Silicon Laboratories 

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D

SFR Definition 9.7. IE: Interrupt Enable

R/W

R/W

R/W

EA

ESPI0

ET2

Bit7

Bit6

Bit5

R/W

ES0

Bit4

R/W

ET1

Bit3

R/W

EX1

Bit2

R/W

R/W

Reset Value

ET0

EX0 00000000

Bit1

Bit0 SFR Address:

(bit addressable) 0xA8

Bit7:

Bit6:

Bit5:

Bit4:

Bit3:

Bit2:

Bit1:

Bit0:

EA: Enable All Interrupts.

This bit globally enables/disables all interrupts. It overrides the individual interrupt mask set-

tings.

0: Disable all interrupt sources.

1: Enable each interrupt according to its individual mask setting.

ESPI0: Enable Serial Peripheral Interface (SPI0) Interrupt.

This bit sets the masking of the SPI0 interrupts.

0: Disable all SPI0 interrupts.

1: Enable interrupt requests generated by SPI0.

ET2: Enable Timer 2 Interrupt.

This bit sets the masking of the Timer 2 interrupt.

0: Disable Timer 2 interrupt.

1: Enable interrupt requests generated by the TF2L or TF2H flags.

ES0: Enable UART0 Interrupt.

This bit sets the masking of the UART0 interrupt.

0: Disable UART0 interrupt.

1: Enable UART0 interrupt.

ET1: Enable Timer 1 Interrupt.

This bit sets the masking of the Timer 1 interrupt.

0: Disable all Timer 1 interrupt.

1: Enable interrupt requests generated by the TF1 flag.

EX1: Enable External Interrupt 1.

This bit sets the masking of External Interrupt 1.

0: Disable external interrupt 1.

1: Enable interrupt requests generated by the INT1 input.

ET0: Enable Timer 0 Interrupt.

This bit sets the masking of the Timer 0 interrupt.

0: Disable all Timer 0 interrupt.

1: Enable interrupt requests generated by the TF0 flag.

EX0: Enable External Interrupt 0.

This bit sets the masking of External Interrupt 0.

0: Disable external interrupt 0.

1: Enable interrupt requests generated by the INT0 input.

Rev. 1.3

91

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