C8051F38B-GMR View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F38B-GMR

Full Speed USB Flash MCU Family

Silicon Laboratories 

C8051F380/1/2/3/4/5/6/7/C

27.3.5. 8-bit Pulse Width Modulator Mode

The duty cycle of the PWM output signal in 8-bit PWM mode is varied using the module's PCA0CPLn cap-

ture/compare register. When the value in the low byte of the PCA counter/timer (PCA0L) is equal to the

value in PCA0CPLn, the output on the CEXn pin will be set. When the count value in PCA0L overflows, the

CEXn output will be reset (see Figure 27.8). Also, when the counter/timer low byte (PCA0L) overflows from

0xFF to 0x00, PCA0CPLn is reloaded automatically with the value stored in the module’s capture/compare

high byte (PCA0CPHn) without software intervention. Setting the ECOMn and PWMn bits in the

PCA0CPMn register enables 8-Bit Pulse Width Modulator mode. If the MATn bit is set to 1, the CCFn flag

for the module will be set each time an 8-bit comparator match (rising edge) occurs. The duty cycle for 8-

Bit PWM Mode is given in Equation 27.2.

Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-

ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the

ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.

Duty Cycle = ---2---5----6----–-----P----2C---5--A--6--0----C-----P----H-----n----

Equation 27.2. 8-Bit PWM Duty Cycle

Using Equation 27.2, the largest duty cycle is 100% (PCA0CPHn = 0), and the smallest duty cycle is

0.39% (PCA0CPHn = 0xFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.

Write to

PCA0CPLn

0

Reset

ENB

Write to

PCA0CPHn ENB

1

PCA0CPHn

PCA0CPMn

PECCMT PE

WC A A A O WC

MO P P T GMC

1 MPN n n n F

6nnn

n

n

0 00x0 x

COVF

PCA0CPLn

Enable

8-bit

Comparator

match S SET Q CEXn Crossbar

R CLR Q

PCA Timebase

PCA0L

Overflow

Figure 27.8. PCA 8-Bit PWM Mode Diagram

Port I/O

306

Rev. 1.4

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