C8051F38B-GMR View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F38B-GMR

Full Speed USB Flash MCU Family

Silicon Laboratories 

C8051F380/1/2/3/4/5/6/7/C

12. Prefetch Engine

The C8051F380/1/2/3/4/5/6/7/C family of devices incorporate a 2-byte prefetch engine. Because the

access time of the Flash memory is 40 ns, and the minimum instruction time is roughly 20 ns, the prefetch

engine is necessary for full-speed code execution. Instructions are read from Flash memory two bytes at a

time by the prefetch engine and given to the CIP-51 processor core to execute. When running linear code

(code without any jumps or branches), the prefetch engine allows instructions to be executed at full speed.

When a code branch occurs, the processor may be stalled for up to two clock cycles while the next set of

code bytes is retrieved from Flash memory. It is recommended that the prefetch be used for optimal code

execution timing.

Note: The prefetch engine can be disabled when the device is in suspend mode to save power.

SFR Definition 12.1. PFE0CN: Prefetch Engine Control

Bit

7

6

5

4

3

2

Name

PFEN

Type

R

R

R/W

R

R

R

Reset

0

0

1

0

0

0

SFR Address = 0xAF; SFR Page = All Pages

Bit Name

Function

7:6 Unused Read = 00b, Write = don’t care.

5 PFEN Prefetch Enable.

This bit enables the prefetch engine.

0: Prefetch engine is disabled.

1: Prefetch engine is enabled.

4:1 Unused Read = 0000b. Write = don’t care.

0 FLBWE Flash Block Write Enable.

This bit allows block writes to Flash memory from software.

0: Each byte of a software Flash write is written individually.

1: Flash bytes are written in groups of two.

1

0

FLBWE

R

R/W

0

0

88

Rev. 1.4

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