C8051F38B-GMR View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F38B-GMR

Full Speed USB Flash MCU Family

Silicon Laboratories 

C8051F380/1/2/3/4/5/6/7/C

PROGRAM/DATA MEMORY

(FLASH)

0x3FFF

0xFF

FLASH

(In-System

Programmable in 512

Byte Sectors)

0x0000

0x80

0x7F

0x30

0x2F

0x20

0x1F

0x00

DATA MEMORY (RAM)

INTERNAL DATA ADDRESS SPACE

Upper 128 RAM

(Indirect Addressing

Only)

Special Function

Register's

(Direct Addressing Only)

(Direct and Indirect

Addressing)

Bit Addressable

General Purpose

Registers

Lower 128 RAM

(Direct and Indirect

Addressing)

0xFFFF

EXTERNAL DATA ADDRESS SPACE

Off-Chip XRAM

(Available only on devices

with EMIF)

0x0800

0x07FF

0x0000

XRAM - 2048 Bytes

(Accessable using MOVX

instruction)

USB FIFOs

1024 Bytes

Figure 13.3. On-Chip Memory Map for 16 kB Devices (C8051F38C)

0x07FF

0x0400

13.1. Program Memory

The CIP-51 core has a 64k-byte program memory space. The C8051F380/1/2/3/4/5/6/7/C implements

64 kB, 32 kB, or 16 kB of this program memory space as in-system, re-programmable Flash memory. Note

that on the C8051F380/1/4/5 (64 kB version), addresses above 0xFBFF are reserved.

Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory

by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature pro-

vides a mechanism for the CIP-51 to update program code and use the program memory space for non-

volatile data storage. Refer to Section “18. Flash Memory” on page 135 for further details.

13.2. Data Memory

The CIP-51 includes 256 of internal RAM mapped into the data memory space from 0x00 through 0xFF.

The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory.

Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations

0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of

eight byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as

bytes or as 128 bit locations accessible with the direct addressing mode.

Rev. 1.4

91

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