C8051F38B-GMR View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
Manufacturer
C8051F38B-GMR Datasheet PDF : 321 Pages
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C8051F380/1/2/3/4/5/6/7/C
SFR Definition 14.2. EMI0CF: External Memory Interface Configuration
Bit
7
6
5
4
3
2
1
0
Name
USBFAE
EMD2
EMD[1:0]
EALE[1:0]
Type
R
R/W
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
1
1
SFR Address = 0x85; SFR Page = All Pages
Bit
Name
Function
7
Unused Read = 0b; Write = don’t care.
6
USBFAE USB FIFO Access Enable.
0: USB FIFO RAM not available through MOVX instructions.
1: USB FIFO RAM available using MOVX instructions. The 1k of USB RAM will be
mapped in XRAM space at addresses 0x0400 to 0x07FF. The USB clock must be
active and greater than or equal to twice the SYSCLK (USBCLK > 2 x
SYSCLK) to access this area with MOVX instructions.
5
Unused Read = 0b; Write = don’t care.
4
EMD2
EMIF Multiplex Mode Select.
0: EMIF operates in multiplexed address/data mode.
1: EMIF operates in non-multiplexed mode (separate address and data pins).
3:2 EMD[1:0] EMIF Operating Mode Select.
These bits control the operating mode of the External Memory Interface.
00: Internal Only: MOVX accesses on-chip XRAM only. All effective addresses
alias to on-chip memory space.
01: Split Mode without Bank Select: Accesses below the on-chip XRAM boundary
are directed on-chip. Accesses above the on-chip XRAM boundary are directed
off-chip. 8-bit off-chip MOVX operations use the current contents of the Address
High port latches to resolve upper address byte. Note that in order to access
off-chip space, EMI0CN must be set to a page that is not contained in the on-chip
address space.
10: Split Mode with Bank Select: Accesses below the on-chip XRAM boundary are
directed on-chip. Accesses above the on-chip XRAM boundary are directed
off-chip. 8-bit off-chip MOVX operations use the contents of EMI0CN to determine
the high-byte of the address.
11: External Only: MOVX accesses off-chip XRAM only. On-chip XRAM is not visi-
ble to the CPU.
1:0 EALE[1:0] ALE Pulse-Width Select Bits (only has effect when EMD2 = 0).
00: ALE high and ALE low pulse width = 1 SYSCLK cycle.
01: ALE high and ALE low pulse width = 2 SYSCLK cycles.
10: ALE high and ALE low pulse width = 3 SYSCLK cycles.
11: ALE high and ALE low pulse width = 4 SYSCLK cycles.
Rev. 1.4
97
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