CRD44800-ST-FB View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CRD44800-ST-FB

6-Channel Digital Amplifier Controller

Cirrus Logic 

7.26 GPIO Pin Level/Edge Trigger (address 2Eh)

7

RESERVED

6

GPIO6_L/E

5

GPIO5_L/E

4

GPIO4_L/E

3

GPIO3_L/E

2

GPIO2_L/E

CS44600

1

GPIO1_L/E

0

GPIO0_L/E

7.26.1 GPIO Level/Edge Input Sensitive (GPIOX_L/E)

Default = 0

Function:

General Purpose Input - This bit defines the GPIO input type (0 = level sensitive, 1 = edge trigger) when

a GPIO pin is configured as an input. The GPIO pin status of an input configured as “edge trigger” is

cleared by reading the GPIO Status Register when not enabled to generate an interrupt (MASK bit equals

0b) and by reset. After a reset this bit defaults to 0b, specifying “level sensitive”.

General Purpose Output - Not Used.

7.27 GPIO Status Register (address 2Fh)

7

6

5

4

3

2

1

0

RESERVED GPIO6_STATUS GPIO5_STATUS GPIO4_STATUS GPIO3_STATUS GPIO2_STATUS GPIO1_STATUS GPIO0_STATUS

7.27.1 GPIO Pin Status (GPIOX_STATUS)

Default = x

Function:

General Purpose Input - Bits in this register are read only when the corresponding GPIO pin is configured

as an input. Each bit indicates the status of the GPIO pin. The corresponding bit of a GPIO input config-

ured as “edge trigger” is cleared by reading the GPIO Status Register. GPIO inputs configured as “level

sensitive” will not be automatically cleared, but will reflect the logic state on the GPIO input. The mask bits

in the GPIO Interrupt Mask Register have no effect on the operation of these status bits.

When a GPIO is un-masked and enabled to generate an interrupt, and is configured as “edge trigger”, a

read operation to this register will clear the status bit and remove the interrupt condition. A read operation

to the Interrupt Status (address 2Ah) (read only) when a GPIO is configured to generate an interrupt con-

dition will not clear any bits in this register.

General Purpose Output - For GPIO pins configured as outputs, these bits are used to control the output

signal level. A 1b written to a particular bit will cause the corresponding GPIO pin to be driven to a logic

high. A 0b will cause a logic low.

DS633F1

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