CRD44800-ST-FB View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CRD44800-ST-FB

6-Channel Digital Amplifier Controller

Cirrus Logic 

CS44600

Power Control (address 02h)” on page 51 to a 1b. Attempts to write this register while the PDN is not set

will be ignored.

Binary Code

MIN_PULSE[4:0]

00000

00110

10100

11111

Minimum Pulse

Setting (multiply by

PWM_MCLK period)

0 - no minimum

6

20

31

Table 14. PWM Minimum Pulse Width Settings

7.31 PWMOUT Delay Register (address 33h)

7

DIFF_DLY2

6

DIFF_DLY1

5

DIFF_DLY0

4

CHNL_DLY4

3

CHNL_DLY3

2

CHNL_DLY2

1

CHNL_DLY1

0

CHNL_DLY0

7.31.1 Differential Signal Delay (DIFF_DLY[2:0])

Default = 000

Function:

The Differential Signal Delay bits allow delay adjustment between each channel’s differential signals,

PWMOUTxx+ and PWMOUTxx-. This set of bits control the delay between PWMOUTxx+ and PW-

MOUTxx- across all active channels. The value of this register determines the amount of delay inserted

in the output path. The effective delay is calculated by multiplying the register value by the period of the

PWM_MCLK. This parameter can only be changed when all modulators and associated logic are in the

power-down state by setting the PDN bit in the register “Clock Configuration and Power Control (address

02h)” on page 51 to a 1b. Attempts to write this register while the PDN is not set will be ignored.

7.31.2

Binary Code

000

001

100

111

Delay Setting (multiply by

PWM_MCLK period)

0 - no delay

1

4

7

Table 15. Differential Signal Delay Settings

Channel Delay Settings (CHNL_DLY[4:0])

Default = 00000

Function:

The Channel Delay bits allow delay adjustment of each of the PWMOUT differential signal pairs, PW-

MOUTAx+/PWMOUTAx- from the associated PWMOUTBx+/PWMOUTBx-. The value of this register de-

termines the amount of delay inserted in the output path. The effective delay is calculated by multiplying

the register value by the period of the PWM_MCLK. This parameter can only be changed when all mod-

ulators and associated logic are in the power-down state by setting the PDN bit in the register “Clock Con-

figuration and Power Control (address 02h)” on page 51 to a 1b. Attempts to write this register while the

PDN is not set will be ignored.

Binary Code

00000

00110

11000

11111

Delay Setting(multiply by PWM_MCLK period)

0 - no delay

6

24

31

Table 16. Channel Delay Settings

68

DS633F1

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