CS495303 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CS495303 Datasheet PDF : 36 Pages
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CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
5.11 Switching Characteristics — Serial Control Port - SPI Master Mode
Parameter
SCP_CLK frequency1,2
SCP_CS falling to SCP_CLK rising 3
Symbol Min
fspisck
-
tspicss
-
Typical
11*DCLKP +
(SCP_CLK PERIOD)/2
Max
Fxtal/2
-
Units
MHz
ns
SCP_CLK low time
tspickl
18
-
ns
SCP_CLK high time
tspickh
18
-
ns
Setup time SCP_MISO input
tspidsu
11
-
ns
Hold time SCP_MISO input
tspidh
5
-
ns
SCP_CLK low to SCP_MOSI output valid
tspidov
-
11
ns
SCP_CLK low to SCP_CS falling
tspicsl
7
-
ns
SCP_CLK low to SCP_CS rising
tspicsh
-
11*DCLKP +
(SCP_CLK PERIOD)/2
-
ns
Bus free time between active SCP_CS
tspicsx
3*DCLKP
-
ns
SCP_CLK falling to SCP_MOSI output high-Z
tspidz
-
20
ns
Y 1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that
the actual maximum speed of the communication port may be limited by the firmware application.
2. See Section 5.8.
R 3. SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer to a
tested parameter
.
INA tspicss
EE_CS
tspicsl
tspickl
0
1
2
6
7
0
5
IM SCP_CLK
fspisck
tspickh
L SCP_MISO
PRE SCP_MOSI
A6
tspidsu
A5
tspidh
A0 R/W MSB
tspidov
MSB
tspicsx
6
7
tspicsh
LSB
LSB
tspidz
Figure 4. Serial Control Port - SPI Master Mode Timing
DS705PP6
Copyright 2009 Cirrus Logic
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