CS495303 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CS495303

Audio Decoder DSP Family with Dual 32-bit DSP Engine Technology

Cirrus Logic 

CS4953xx Data Sheet

32-bit Audio Decoder DSP Family

5.13 Switching Characteristics — Serial Control Port - I2C Master Mode

SCP_CLK frequency1

Parameter

SCP_CLK low time

SCP_CLK high time

SCP_SCK rising to SCP_SDA rising or falling for START or STOP

condition

Symbol

fiicck

tiicckl

tiicckh

tiicckcmd

Min

-

1.25

1.25

1.25

Max

Units

400

kHz

-

µs

-

µs

µs

START condition to SCP_CLK falling

tiicstscl

1.25

-

µs

SCP_CLK falling to STOP condition

tiicstp

2.5

-

µs

Bus free time between STOP and START conditions

tiicbft

3

-

µs

Setup time SCP_SDA input valid to SCP_CLK rising

tiicsu

100

ns

Hold time SCP_SDA input after SCP_CLK falling

SCP_CLK low to SCP_SDA out valid

tiich

20

tiicdov

-

-

ns

36

ns

1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that

the actual maximum speed of the communication port may be limited by the firmware application.

RY tiicckcmd

A SCP_CLK

tiicstscl

IN SCP_SDA

tiicckl

tiicr

01

6

7

tiicf

8

01

tiicckcmd

6

7

8

tiicckh

tiicdov

fiicck

A6

A0 R/W ACK MSB

tiicstp

LSB ACK

tiicbft

tiicsu

tiich

PRELIM Figure 6. Serial Control Port - I2C Master Mode Timing

DS705PP6

Copyright 2009 Cirrus Logic

17

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