CS495303 View Datasheet(PDF) - Cirrus Logic
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Description
Manufacturer
CS495303 Datasheet PDF : 36 Pages
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CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
5.18 Switching Characteristics — Digital Audio Output Port
Parameter
Symbol
Min
Max
Unit
DAO_MCLK period
DAO_MCLK duty cycle
DAO_SCLK period for Master or Slave mode1
DAO_SCLK duty cycle for Master or Slave mode1
Tdaomclk
40
-
45
Tdaosclk
40
-
40
-
ns
55
%
-
ns
60
%
Master Mode (Output A1 Mode)1,2
DAO_SCLK delay from DAO_MCLK rising edge,
DAO_MCLK as an input
tdaomsck
-
19
ns
DAO_SCLK delay from DAO_LRCLK transition, respectively3
tdaomlrts
-
8
ns
DAO_LRCLK delay from DAO_SCLK transition, respectively3
tdaomstlr
-
8
DAO1_DATA[3..0], DAO2_DATA[1..0]
delay from DAO_SCLK transition3
tdaomdv
-
10
Slave Mode (Output A0 Mode)4
DAO1_DATA[3..0], DAO2_DATA[1..0]
Y delay from DAO_SCLK transition3
tdaosdv
-
15
DAO_LRCLK delay from DAO_SCLK transition, respectively3
tdaosstlr
-
30
DAO_SCLK delay from DAO_LRCLK transition, respectively3
tdaoslrts
-
15
R 1. Master mode timing specifications are characterized, not production tested.
2. Master mode is defined as the CS4953xx driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is
A divided to produce DAO_SCLK, DAO_LRCLK.
3. This timing parameter is defined from the non-active edge of DAO_SCLK. The active edge of DAO_SCLK is the
point at which the data is valid.
4. Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.
IMIN DAO_MCLK
L DAO_SCLK
tdaomdv
E DAOn_DATAn
PR DAO_LRCLK
tdaomlclk
tdaomsck
tdaomlrts
DAO_MCLK
DAO_SCLK
DAOn_DATAn
DAO_LRCLK
tdaomclk
tdaomsck
tdaomstlr
ns
ns
ns
ns
ns
Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK
Figure 13. Digital Audio Port Output Timing Master Mode
24
Copyright 2009 Cirrus Logic
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