CS8952(2001) View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CS8952 Datasheet PDF : 82 Pages
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CS8952
6.16 PCS Sub-Layer Configuration Register - Address 17h
15
NRZI Enable
14
Time-Out
Select
13
Time-Out
Disable
7
6
5
CLK25 Disable Enable LT/100 CIM Disable
12
Repeater
Mode
4
Tx Disable
11
LED5 Mode
3
Rx Disable
10
9
Unlock Regs
MR Preamble
Enable
8
Fast Test
2
1
0
LED1 Mode LED4 Mode Digital Reset
BIT
NAME
15 NRZI Enable
14 Time-Out Select
13 Time-Out Disable
12 Repeater Mode
11 LED5 Mode
TYPE
RESET
DESCRIPTION
Read/Write 1
When this bit is set, the NRZI encoder and decoder
are enabled. When this bit is clear, NRZI encoding
and decoding are disabled.
Read/Write 0
When this bit is set, the time-out counter in the
receive descrambler is set to time-out after 2 ms
without IDLES. When clear the counter is set to time-
out after 722 µs without IDLES.
Read/Write 0
When this bit is set, the time-out counter in the
receive descrambler is disabled. When this bit is
clear, the time-out counter is enabled.
Read/Write Reset to the value This bit defines the mode of the Carrier Sense (CRS)
on the
signal. When this bit is set, CRS is asserted due to
REPEATER pin. receive activity only. When this bit is clear, CRS is
asserted due to either transmit or receive activity.
Read/Write 0
This bit defines the mode of Pin LED5. When this bit
is set, pin LED5 indicates the synchronization status
of the 100BASE-TX descrambler. When this bit is
clear, LED5 indicates a collision.
10 Unlock Regs
Read/Write 0
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, this bit unlocks certain read only control
registers for factory testing. Leave clear for proper
operation.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
53
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