CS8952(2001) View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CS8952 Datasheet PDF : 82 Pages
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CS8952
6.18 Self Status Register - Address 19h
15
Link OK
7
Full Duplex
14
Power
Down
6
10BASE-T
Mode
13
Receiving
Data
5
CIM Status
12
Descrambler
Lock
4
11
10
Disable CRS Auto-Neg
on Time-out Enable Status
3
2
PHY Address
9
PAUSE
1
8
FEFI Enable
0
BIT
NAME
15 Link OK
14 Power Down
13 Receiving Data
12 Descrambler Lock
11 Disable CRS on
Time-out
10 Auto-Neg Enable
Status
9
PAUSE
8
FEFI Enable
7
Full Duplex
6
10BASE-T Mode
TYPE
RESET
DESCRIPTION
Read Only 0
When set, this bit indicates that a valid link connec-
tion has been detected. The type of link established
may be determined from bits 6, 7, and 9. When clear,
this bit indicates that a valid link connection does not
exist. This bit may be used to determine the current
status of the link.
Read Only 1
When high, this bit indicates that the CS8952 is in a
low power state.
Read Only 0
This bit is high whenever the CS8952 is receiving
valid data. It is a direct copy of the state of the
RX_DV pin accessible by software.
Read Only 0
When high, this bit indicates that the descrambler
has successfully locked to the scrambler seed of the
far-end transmitter and is able to descramble
received data.
Read/Write Reset to the logic This bit controls the state of the CRS pin upon a
inverse of the
descrambler time-out. When set, CRS will be forced
value on the
low upon a descrambler time-out, and will not be
REPEATER pin. released until the descrambler has re-acquired syn-
chronization.
Read Only If auto-negotiation This bit reflects the value of bit 12 in the Basic Mode
is enabled via the Control Register (address 00h). When set, it indi-
AN[1:0] pins, reset cates that auto-negotiation has been enabled. When
to 1; otherwise, clear, this bit indicates that the mode of the CS8952
reset to 0.
has been forced to that indicated by bits 6, and 7.
Read Only 0
When set, this bit indicates that the Flow-Control
PAUSE function has been negotiated. This indicates
that both the local device and the link partner have
advertised this capability.
Read/Write 0
This bit controls the Far-End Fault Generate and
Detect state machines. When this bit is set and auto-
negotiation is disabled (bit 10 is clear), both state
machines are enabled. When clear, this bit disables
both state machines.
Read Only If a full duplex When set, this bit indicates that the CS8952 has
mode is enabled been configured for Full-Duplex operation.
via the AN[1:0]
pins, reset to 1;
otherwise, reset to
0.
Read Only 0
When set, this bit indicates that the CS8952 has
been configured for 10 Mb/s operation.
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
59
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