CS98100
4.3 Internal IO Space Map
Table 11 shows how the Internal IO space is mapped between general registers, internal SRAM ports, and
the RISC processor debug port.
Byte address offset
Description
0_0000 – 0_2FFF
General registers
0_3000 – 1_FFFF
General Internal SRAM
2_0000 – 2_FFFF
RISC Internal SRAM/Registers
Table 11. Internal IO Space Map
4.4 CS98100 Register Space
Table 12 lists the register groups, and how they are split among the main CS98100 functional blocks.
CS98100 Register
Block
000xx, 010xx
General
001xx
Host
002xx
DRAM Controller (DRC)
003xx
DMA
004xx
CD/DVD Interface
005xx
Serial DVD (DVDS)
006xx
DSP
007xx
Sync Control
008xx
MPEG Video Decoder
00Axx
Picture-in-picture
00Bxx
Video Processor
00Cxx
Subpicture Display
00Dxx
On-screen Display
00Exx
PCM In/Out
02xxxx
RISC Processor
Table 12. CS98100 Register Map and Blocks
Table 13 lists all the registers for the CS98100 and their addresses, and indicates whether the registers are
read/write (R/W), read only (RO) or write only (WO).
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