DSPIC30F1013AT-30E/ML View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

DSPIC30F1013AT-30E/ML

High-Performance, 16-Bit Digital Signal Controllers

Microchip Technology 

dsPIC30F3014/4013

20.4 Reset

The PIC18F1220/1320 differentiates between various

kinds of Reset:

a) Power-on Reset (POR)

b) MCLR Reset during normal operation

c) MCLR Reset during Sleep

d) Watchdog Timer (WDT) Reset (during normal

operation)

e) Programmable Brown-out Reset (BOR)

f) RESET Instruction

g) Reset caused by trap lockup (TRAPR)

h) Reset caused by illegal opcode or by using an

uninitialized W register as an Address Pointer

(IOPUWR)

Different registers are affected in different ways by var-

ious Reset conditions. Most registers are not affected

by a WDT wake-up since this is viewed as the resump-

tion of normal operation. Status bits from the RCON

register are set or cleared differently in different Reset

situations, as indicated in Table 20-5. These bits are

used in software to determine the nature of the Reset.

A block diagram of the On-Chip Reset Circuit is shown

in Figure 20-2.

A MCLR noise filter is provided in the MCLR Reset

path. The filter detects and ignores small pulses.

Internally generated Resets do not drive MCLR pin low.

FIGURE 20-2:

RESET SYSTEM BLOCK DIAGRAM

RESET

Instruction

MCLR

Digital

Glitch Filter

Sleep or Idle

WDT

Module

VDD Rise

Detect

POR

VDD

Brown-out

Reset

BOREN

Trap Conflict

BOR

S

R

Q

SYSRST

Illegal Opcode/

Uninitialized W Register

20.4.1 POR: POWER-ON RESET

A power-on event generates an internal POR pulse

when a VDD rise is detected. The Reset pulse occurs at

the POR circuit threshold voltage (VPOR) which is nom-

inally 1.85V. The device supply voltage characteristics

must meet specified starting voltage and rise rate

requirements. The POR pulse resets a POR timer and

places the device in the Reset state. The POR also

selects the device clock source identified by the

oscillator configuration fuses.

The POR circuit inserts a small delay, TPOR, which is

nominally 10 μs and ensures that the device bias

circuits are stable. Furthermore, a user selected power-

up time-out (TPWRT) is applied. The TPWRT parameter

is based on device Configuration bits and can be 0 ms

(no delay), 4 ms, 16 ms, or 64 ms. The total delay is at

device power-up, TPOR + TPWRT. When these delays

have expired, SYSRST is negated on the next leading

edge of the Q1 clock and the PC jumps to the Reset

vector.

The timing for the SYSRST signal is shown in

Figure 20-3 through Figure 20-5.

© 2007 Microchip Technology Inc.

DS70138E-page 145

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