DSPIC30F4013AT-20E/ML-ES View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
DSPIC30F4013AT-20E/ML-ES Datasheet PDF : 220 Pages
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dsPIC30F3014/4013
a single SPI clock cycle. When Frame Synchronization
is enabled, the data transmission starts only on the
subsequent transmit edge of the SPI clock.
FIGURE 15-1:
SPI BLOCK DIAGRAM
Read
Internal
Data Bus
Write
SPIxBUF
Receive
SPIxBUF
Transmit
SDIx
SPIxSR
bit 0
SDOx
SSx
SS and
FSYNC
Control
Shift
Clock
Clock
Control
Edge
Select
SCKx
Note: x = 1 or 2.
Secondary
Prescaler
1:1-1:8
Primary
Prescaler
FCY
1:1, 1:4,
1:16, 1:64
Enable Master Clock
FIGURE 15-2:
SPI MASTER/SLAVE CONNECTION
SPI Master
Serial Input Buffer
(SPIxBUF)
SDOx
SDIy
SPI Slave
Serial Input Buffer
(SPIyBUF)
Shift Register
(SPIxSR)
MSb
LSb
PROCESSOR 1
SDIx
Serial Clock
SCKx
SDOy
Shift Register
(SPIySR)
MSb
LSb
SCKy
PROCESSOR 2
Note: x = 1 or 2, y = 1 or 2.
DS70138E-page 94
© 2007 Microchip Technology Inc.
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