JS28F256J3A-125 View Datasheet(PDF) - Intel
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JS28F256J3A-125 Datasheet PDF : 72 Pages
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256-Mbit J3 (x8/x16)
Figure 17. Protection Register Memory Map
Word
Address
A[24:1]: 256 Mbit A[22:1]: 64 Mbit
A[23:1]: 128 Mbit A[21:1]: 32 Mbit
0x88
0x85
0x84
0x81
64-bit Segment
(User-Programmable)
128-Bit Protection Register 0
64-bit Segment
(Factory-Programmed)
Lock Register 0
0x80 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NOTE: A0 is not used in x16 mode when accessing the Protection Register map (See Table 8 for x16
addressing). For x8 mode A0 is used (See Table 21 for x8 addressing).
Table 20. Word-Wide Protection Register Addressing
Word Use
A8
A7
A6
A5
A4
A3
A2
A1
LOCK Both
1
0
0
0
0
0
0
0
0
Factory
1
0
0
0
0
0
0
1
1
Factory
1
0
0
0
0
0
1
0
2
Factory
1
0
0
0
0
0
1
1
3
Factory
1
0
0
0
0
1
0
0
4
User
1
0
0
0
0
1
0
1
5
User
1
0
0
0
0
1
1
0
6
User
1
0
0
0
0
1
1
1
7
User
1
0
0
0
1
0
0
0
Table 21. Byte-Wide Protection Register Addressing (Sheet 1 of 2)
Byte
Use
A8
A7
A6
A5
A4
A3
A2
A1
A0
LOCK Both
1
0
0
0
0
0
0
0
0
LOCK Both
1
0
0
0
0
0
0
0
1
0
Factory
1
0
0
0
0
0
0
1
0
1
Factory
1
0
0
0
0
0
0
1
1
2
Factory
1
0
0
0
0
0
1
0
0
3
Factory
1
0
0
0
0
0
1
0
1
4
Factory
1
0
0
0
0
0
1
1
0
5
Factory
1
0
0
0
0
0
1
1
1
48
Datasheet
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