RC28F640J3C-125 View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

RC28F640J3C-125

Intel StrataFlash® Memory (J3)

Intel 

256-Mbit J3 (x8/x16)

Table 31. Protection Register Information

Offset(1)

P = 31h

Length

Description

(Optional Flash Features and Commands)

(P+E)h

1

Number of Protection register fields in JEDEC ID space.

“00h,” indicates that 256 protection bytes are available

(P+F)h

(P+10)h

(P+11)h

(P+12)h

Protection Field 1: Protection Description

This field describes user-available One Time Programmable

(OTP) Protection Register bytes. Some are pre-programmed

with device-unique serial numbers. Others are user-

programmable. Bits 0-15 point to the Protection Register lock

4 byte, the section’s first byte. The following bytes are factory

pre-programmed and user-programmable.

bits 0-7 = Lock/bytes JEDEC-plane physical low address

bits 8-15 = Lock/bytes JEDEC-plane physical high address

bits 16-23 = “n” such that 2n = factory pre-programmed bytes

bits 24-31 = “n” such that 2n = user-programmable bytes

NOTE:

1. The variable P is a pointer which is defined at CFI offset 15h.

Add.

3F:

40:

41:

42:

43:

Hex

Code

--01

--80

--00

--03

--03

Value

01

80h

00h

8bytes

8bytes

Table 32. Burst Read Information

Offset(1)

P = 31h

Length

Description

(Optional Flash Features and Commands)

Page Mode Read capability

(P+13)h

bits 0–7 = “n” such that 2n HEX value represents the number

1

of read-page bytes. See offset 28h for device word width to

determine page-mode data output width. 00h indicates no

read page buffer.

(P+14)h

1

Number of synchronous mode read configuration fields that

follow. 00h indicates no burst capability.

(P+15)h

Reserved for future use

NOTE:

1. The variable P is a pointer which is defined at CFI offset 15h.

Add.

Hex

Code

Value

44: --03 8 byte

45: --00

0

46:

58

Datasheet

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