256-Mbit J3 (x8/x16)
Figure 19. Status Register Flowchart
Start
Command Cycle
- Issue Status Register Command
- Address = any dev ice address
- Data = 0x70
Data Cycle
- Read Status Register SR[7:0]
- Set/Reset
by WSM
- Set by WSM
- Reset by user
- See Clear Status
Register
Command
SR7 = '1'
No
Y es
SR6 = '1'
Y es
Erase Suspend
See Suspend/Resume Flowchart
No
SR2 = '1'
Y es
Program Suspend
See Suspend/Resume Flowchart
No
SR5 = '1'
Y es
No
Y es
SR4 = '1'
No
SR4 = '1'
Y es
No
Error
Erase Failure
Error
Program Failure
Error
Command Sequence
Y es
SR3 = '1'
No
Error
V PEN < VPENLK
SR1 = '1'
Y es
No
Error
Block Locked
End
60
0606_07A
Datasheet