FDC37B72X View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
Manufacturer
FDC37B72X Datasheet PDF : 238 Pages
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PDATA<7:0>
nACK
nAUTOFD
t2
t1
t5
t6
t4
t3
t4
FIGURE 30 - ECP PARALLEL PORT REVERSE TIMING
NAME
t1
t2
t3
t4
t5
t6
TABLE 98 - ECP PARALLEL PORT REVERSE TIMING
DESCRIPTION
MIN TYP
PDATA Valid to nACK Asserted
0
nAUTOFD Deasserted to PDATA Changed
0
nACK Asserted to nAUTOFD Deasserted
80
(Notes 1,2)
nACK Deasserted to nAUTOFD Asserted (Note 2)
80
nAUTOFD Asserted to nACK Asserted
0
nAUTOFD Deasserted to nACK Deasserted
0
MAX
200
UNITS
ns
ns
ns
200
ns
ns
ns
Note 1: Maximum value only applies if there is room in the FIFO and terminal count has not been
received. ECP can stall by keeping nAUTOFD low.
Note 2: nACK is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns.
232
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