FDC37B72X View Datasheet(PDF) - SMSC -> Microchip
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FDC37B72X Datasheet PDF : 238 Pages
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TABLE 92 - EPP 1.9 DATA OR ADDRESS WRITE CYCLE TIMING
DESCRIPTION
MIN TYP MAX
nIOW Asserted to PDATA Valid
0
50
nWAIT Asserted to nWRITE Change (Note 1)
60
185
nWRITE to Command Asserted
5
35
nWAIT Deasserted to Command Deasserted
60
190
(Note 1)
nWAIT Asserted to PDATA Invalid (Note 1)
0
Time Out
10
12
Command Deasserted to nWAIT Asserted
0
SDATA Valid to nIOW Asserted
10
nIOW Deasserted to DATA Invalid
0
nIOW Asserted to IOCHRDY Asserted
0
24
nWAIT Deasserted to IOCHRDY Deasserted
60
160
(Note 1)
IOCHRDY Deasserted to nIOW Deasserted
10
nIOW Asserted to nWRITE Asserted
0
70
nWAIT Asserted to Command Asserted (Note 1)
60
210
Command Asserted to nWAIT Deasserted
0
10
PDATA Valid to Command Asserted
10
Ax Valid to nIOW Asserted
40
nIOW Asserted to Ax Invalid
10
nIOW Deasserted to nIOW or nIOR Asserted
40
nWAIT Asserted to nWRITE Asserted (Note 1)
60
185
nWAIT Asserted to PDIR Low
0
PDIR Low to nWRITE Asserted
0
UNITS
ns
ns
ns
ns
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
s
ns
ns
ns
ns
ns
ns
ns
Note 1: nWAIT must be filtered to compensate for ringing on the parallel bus cable. WAIT is considered
to have settled after it does not transition for a minimum of 50 nsec.
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