FDC37B72X View Datasheet(PDF) - SMSC -> Microchip
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Description
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FDC37B72X Datasheet PDF : 238 Pages
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TABLE 95 - EPP 1.7 DAT OR ADDRESS READ CYCLE TIMING
DESCRIPTION
MIN TYP MAX
nIOR Deasserted to Command Deasserted
50
nWAIT Asserted to IOCHRDY Deasserted
0
40
Command Deasserted to PDATA Hi-Z
0
Command Asserted to PDATA Valid
0
nIOR Asserted to IOCHRDY Asserted
24
nWAIT Deasserted to IOCHRDY Deasserted
50
IOCHRDY Deasserted to nIOR Deasserted
0
nIOR Deasserted to SDATA High-Z (Hold Time)
0
40
PDATA Valid to SDATA Valid
40
Time Out
10
12
Ax Valid to nIOR Asserted
40
nIOR Deasserted to Ax Invalid
10
Command Deasserted to nWAIT Deasserted
0
nIOR Deasserted to nIOW or nIOR Asserted
40
nIOR Asserted to Command Asserted
55
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
ns
ns
ns
Note: WRITE is controlled by setting the PDIR bit to "1" in the control register before performing an EPP
Read.
228
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