GS8170DW72C-200 View Datasheet(PDF) - Giga Semiconductor

Part Name

Description

Manufacturer

GS8170DW72C-200

18Mb Σ1x1Dp CMOS I/O Double Late Write SigmaRAM™

Giga Semiconductor 

GS8170DW36/72C-333/300/250/200

JTAG Port Recommended Operating Conditions and DC Characteristics

Parameter

Symbol

Min.

Max.

Unit Notes

1.8 V Test Port Input High Voltage

VIHJ2

0.6 * VDD

VDD +0.3

V

1

1.8 V Test Port Input Low Voltage

TMS, TCK and TDI Input Leakage Current

TMS, TCK and TDI Input Leakage Current

TDO Output Leakage Current

VILJ2

–0.3

IINHJ

–300

IINLJ

–1

IOLJ

–1

0.3 * VDD

1

100

1

V

1

uA

2

uA

3

uA

4

Test Port Output High Voltage

VOHJ

1.7

—

V 5, 6

Test Port Output Low Voltage

VOLJ

—

0.4

V 5, 7

Test Port Output CMOS High

VOHJC VDDQ – 100 mV

—

V 5, 8

Test Port Output CMOS Low

VOLJC

—

100 mV

V 5, 9

Notes:

1. Input Under/overshoot voltage must be –2 V > Vi < VDDn +2 V not to exceed 2.5 V maximum, with a pulse width not to exceed 20% tTKC.

2. VILJ ≤ VIN ≤ VDDn

3. 0 V ≤ VIN ≤ VILJn

4. Output Disable, VOUT = 0 to VDDn

5. The TDO output driver is served by the VDDQ supply.

6. IOHJ = –4 mA

7. IOLJ = + 4 mA

8. IOHJC = –100 uA

9. IOHJC = +100 uA

JTAG Port Timing Diagram

TCK

TDI

TMS

TDO

Parallel SRAM input

tTKC

tTKH

tTH

tTS

tTH

tTS

tTKQ

tTH

tTS

tTKL

Rev: 2.04 5/2005

24/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

© 2002, GSI Technology, Inc.

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