ISPGDX160V-3Q208I View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
ISPGDX160V-3Q208I Datasheet PDF : 36 Pages
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Specifications ispGDX160V/VA
ispLEVER Development System
signals are fed into the on-chip programming circuitry
where a state machine controls the programming.
The ispLEVER Development System supports ispGDX
design using a VHDL or Verilog language syntax. From On-chip programming can be accomplished using an
creation to in-system programming, the ispLEVER sys- IEEE 1149.1 boundary scan protocol. The IEEE 1149.1-
tem is an easy-to-use, self-contained design tool.
Features
S • VHDL and Verilog Synthesis Support Available
• ispGDX Design Compiler
- Design Rule Checker
E - I/O Connectivity Checker
- Automatic Compiler Function
• Industry Standard JEDEC File for Programming
IC • Min/Max Timing Report
D • Interfaces To Popular Timing Simulators
• User Electronic Signature (UES) Support
V E • Detailed Log and Report Files For Easy Design
Debug
E • On-line Help
U • Windows® XP, Windows 2000, Windows 98 and
Windows NT® Compatible
D IN • Solaris® and HP-UX Versions Available
In-System Programmability
T T All necessary programming of the ispGDXV/VA is done
via four TTL level logic interface signals. These four
compliant interface signals are Test Data In (TDI), Test
Data Out (TDO), Test Clock (TCK) and Test Mode Select
(TMS) control. The EPEN pin is also used to enable or
disable the JTAG port.
The embedded controller port enable pin (EPEN) is used
to enable the JTAG tap controller and in that regard has
similar functionality to a TRST pin. When the pin is driven
high, the JTAG TAP controller is enabled. This is also true
when the pin is left unconnected, in which case the pin is
pulled high by the permanent internal pullup. This allows
ISP programming and BSCAN testing to take place as
specified by the Instruction Table.
When the pin is driven low, the JTAG TAP controller is
driven to a reset state asynchronously. It stays there
while the pin is held low. After pulling the pin high the
JTAG controller becomes active. The intent of this fea-
ture is to allow the JTAG interface to be directly controlled
by the data bus of an embedded controller (hence the
name Embedded Port Enable). The EPEN signal is used
as a “device select” to prevent spurious programming
and/or testing from occuring due to random bit patterns
on the data bus. Figure 9 illustrates the block diagram for
the ispJTAG™ interface.
C N Figure 9. ispJTAG Device Programming Interface
E TDO
O TDI
LTMS
TCK
ispJTAG
Programming
Interface
SE DISC EPEN
ispGDX
160V/VA
Device
ispLSI
Device
ispMACH
Device
ispGDX
160V/VA
Device
ispGDX
160V/VA
Device
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