M48T251VPM View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M48T251VPM

5.0 or 3.3V, 4096K TIMEKEEPER® SRAM with PHANTOM

STMicroelectronics 

M48T251Y, M48T251V

WRITE

WRITE Mode (see Figure 6.) occurs whenever CE

and WE signals are low (after address inputs are

stable). The most recent falling edge of CE and

WE will determine when the WRITE cycle begins

(the earlier, rising edge of CE or WE determines

cycle termination). All address inputs must be kept

stable throughout the WRITE cycle. WE must be

Figure 6. Memory WRITE Cycle 1

high (inactive) for a minimum recovery time (tWR)

before a subsequent cycle is initiated. The OE

control signal should be kept high (inactive) during

the WRITE cycles to avoid bus contention. If CE

and OE are low (active), WE will disable the out-

puts for Output Data WRITE Time (tODW) from its

falling edge.

ADDRESSES

tWC

tAW

CE

WE

DQ0–DQ7

tWR

tWP

tODW

tOEW

HIGH IMPEDANCE

tDS

tDH

DATA IN

STABLE

AI04231

Note: 1. OE = VIH or VIL. If OE = VIH during a WRITE cycle, the output buffers remain in a high impedance state.

2. If the CE low transition occurs simultaneously with or later than the WE low transition in WRITE Cycle 1, the output buffers remain

in a high impedance state during this period.

3. If the CE high transition occurs simultaneously with the WE high transition, the output buffers remain in a high impedance state

during this period.

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