Registers description
Table 33.
HR
ST1-ST0
SIM
CTRL_REG4 description (continued)
High resolution output mode: Default value: 0
(0: High resolution disable; 1: High resolution Enable)
Self test enable. Default value: 00
(00: Self test disabled; Other: See Table 34)
SPI serial interface mode selection. Default value: 0
(0: 4-wire interface; 1: 3-wire interface).
Table 34. Self test mode configuration
ST1
ST0
Self test mode
0
0
Normal mode
0
1
Self test 0
1
0
Self test 1
1
1
--
LIS3DH
8.12
CTRL_REG5 (24h)
Table 35. CTRL_REG5 register
BOOT FIFO_EN --
-- LIR_INT1 D4D_INT1
0
0
Table 36. CTRL_REG5 description
BOOT
Reboot memory content. Default value: 0
(0: normal mode; 1: reboot memory content)
FIFO_EN
FIFO enable. Default value: 0
(0: FIFO disable; 1: FIFO Enable)
LIR_INT1
Latch interrupt request on INT1_SRC register, with INT1_SRC register
cleared by reading INT1_SRC itself. Default value: 0.
(0: interrupt request not latched; 1: interrupt request latched)
D4D_INT1
4D enable: 4D detection is enabled on INT1 when 6D bit on INT1_CFG is set
to 1.
8.13
CTRL_REG6 (25h)
Table 37. CTRL_REG6 register
I2_CLICKen I2_INT1 0
BOOT_I1 0
--
H_LACTIVE -
8.14 REFERENCE/DATACAPTURE (26h)
Table 38. REFERENCE register
Ref7
Ref6
Ref5
Ref4
Ref3
Ref2
Ref1
Ref0
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Doc ID 17530 Rev 1