Registers description
LIS3DH
Table 50. INT1_SRC description
Y low. Default value: 0
YL
(0: no interrupt, 1: Y Low event has occurred)
X high. Default value: 0
XH
(0: no interrupt, 1: X High event has occurred)
X low. Default value: 0
XL
(0: no interrupt, 1: X Low event has occurred)
Interrupt 1 source register. Read only register.
Reading at this address clears INT1_SRC IA bit (and the interrupt signal on INT 1 pin) and
allows the refreshment of data in the INT1_SRC register if the latched option was chosen.
8.23
INT1_THS (32h)
Table 51. INT1_THS register
0
THS6
THS5
THS4
THS3
THS2
Table 52. INT1_THS description
THS6 - THS0 Interrupt 1 threshold. Default value: 000 0000
THS1
THS0
8.24 INT1_DURATION (33h)
Table 53. INT1_DURATION register
0
D6
D5
D4
D3
D2
D1
D0
Table 54. INT1_DURATION description
D6 - D0
Duration value. Default value: 000 0000
D6 - D0 bits set the minimum duration of the Interrupt 1 event to be recognized. Duration
steps and maximum values depend on the ODR chosen.
8.25 CLICK_CFG (38h)
Table 55. CLICK_CFG register
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ZD
ZS
YD
YS
XD
XS
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