ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A)
ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Figure 117. SCI-A Block Diagram
TDO
RDI
Write
Transmit Data Register (TDR)
Read
(DATA REGISTER) SCIDR
Received Data Register (RDR)
Transmit Shift Register
Received Shift Register
SCICR1
R8 T8 SCID M WAKE PCE PS PIE
TRANSMIT
CONTROL
WAKE
UP
UNIT
SCICR2
TIE TCIE RIE ILIE TE RE RWU SBK
RECEIVER
CONTROL
RECEIVER
CLOCK
SCISR
TDRE TC RDRF IDLE OR NF FE PE
SCI
INTERRUPT
CONTROL
TRANSMITTER
CLOCK
fCPU
/16
/PR
SCICR3
- LINE - - - - - -
Extended Prescaler
Block Diagram
(cf.Figure 119)
TRANSMITTER RATE
CONTROL
SCIBRR
SCP1SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
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