ST92150CR1TC View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST92150CR1TC

8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E³ ™ (EMULATED EEPROM), CAN 2.0B AND J1850 BLPD

STMicroelectronics 

I2C BUS INTERFACE (Cont’d)

Figure 126. I2C Interface Block Diagram

SDA

DATA

CONTROL

SCL

CLOCK

CONTROL

I2C BUS INTERFACE

DATA BUS

DATA REGISTER

DATA SHIFT REGISTER

COMPARATOR

OWN ADDRESS REGISTER 1

OWN ADDRESS REGISTER 2

GENERAL CALL ADDRESS

CLOCK CONTROL REGISTER

STATUS REGISTER 1

STATUS REGISTER 2

CONTROL REGISTER

DMA

LOGIC AND INTERRUPT/DMA REGISTERS

CONTROL SIGNALS

INTERRUPT

VR02119A

10.8.3 Functional Description

Refer to the I2CCR, I2CSR1 and I2CSR2 registers

in Section 10.8.7. for the bit definitions.

The I2C interface works as an I/O interface

between the ST9 microcontroller and the I2C bus

protocol. In addition to receiving and transmitting

data, the interface converts data from serial to

parallel format and vice versa using an interrupt or

polled handshake.

It operates in Multimaster/slave I2C mode. The se-

lection of the operating mode is made by software.

The I2C interface is connected to the I2C bus by a

data pin (SDA) and a clock pin (SCL) which must

be configured as open drain when the I2C cell is

enabled by programming the I/O port bits and the

PE bit in the I2CCR register. In this case, the value

of the external pull-up resistance used depends on

the application.

When the I2C cell is disabled, the SDA and SCL

ports revert to being standard I/O port pins.

The I2C interface has sixteen internal registers.

Six of them are used for initialization:

– Own Address Registers I2COAR1, I2COAR2

– General Call Address Register I2CADR

– Clock Control Registers I2CCCR, I2CECCR

– Control register I2CCR

The following four registers are used during data

transmission/reception:

– Data Register I2CDR

– Control Register I2CCR

– Status Register 1 I2CSR1

– Status Register 2 I2CSR2

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