I2C BUS INTERFACE
I2C BUS INTERFACE (Cont’d)
Figure 128. Transfer Sequencing
7-bit Slave receiver:
S Address A
Data1
EV1
A
Data2
EV2
A
DataN
.....
EV2
A
P
EV2
EV4
7-bit Slave transmitter:
S Address A
Data1
EV1 EV3
A
Data2
EV3
A
DataN
.....
EV3
NA
P
EV3-1
EV4
7-bit Master receiver:
S
Address A
EV5
EV6
Data1
A
Data2
EV7
A
.....
EV7
DataN NA
P
EV7
7-bit Master transmitter:
S
Address A
EV5
EV6 EV8
Data1
A
Data2
EV8
A
.....
EV8
DataN
A
P
EV8
10-bit Slave receiver:
S Header A Address A
Data1
EV1
A
DataN
.....
EV2
A
P
EV2
EV4
10-bit Slave transmitter:
Sr Header A
Data1 A
.... DataN A
P
EV1 EV3
EV3 .
EV3-1
EV4
10-bit Master transmitter
S
Header A
Address
EV5
EV9
A
EV6 EV8
Data1
A
.....
EV8
DataN
A
P
EV8
10-bit Master receiver:
Sr
Header A
Data1
EV5
EV6
A
.....
EV7
DataN
A
P
EV7
Legend:
S=Start, Sr = Repeated Start, P=Stop, A=Acknowledge, NA=Non-acknowledge,
EVx=Event (with interrupt if ITE=1)
EV1: EVF=1, ADSL=1, cleared by reading SR1 register.
EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register or when DMA
is complete.
EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register or when DMA
is complete.
EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading SR1 register, BTF is cleared by releasing the
lines (STOP=1, STOP=0) or writing DR register (for example DR=FFh). Note: If lines are released by
STOP=1, STOP=0 the subsequent EV4 is not seen.
EV4: EVF=1, STOPF=1, cleared by reading SR2 register.
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