LTC1096AI(RevB) View Datasheet(PDF) - Linear Technology

Part Name

Description

Manufacturer

LTC1096AI
(Rev.:RevB)

Micropower Sampling 8-Bit Serial I/O A/D Converters

Linear Technology 

LTC1096/LTC1096L

LTC1098/LTC1098L

APPLICATI S I FOR

MSB-FIRST DATA (MSBF = 1)

ATIO

tCYC

CS

CLK

tsuCS

DIN

DOUT

tWAKEUP

POWER

DOWN

START

ODD/

SIGN

DON'T CARE

SGL/

MSBF

DIFF

HI-Z

NULL

Hi-Z

BIT B7 B6 B5 B4 B3 B2 B1 B0*

tSMPL

(MSB)

tCONV

MSB-FIRST DATA (MSBF = 0)

tCYC

CS

tWAKEUP

POWER

DOWN

CLK

tsuCS

START

ODD/

SIGN

DIN

HI-Z

DOUT

SGL/

DIFF

tSMPL

MSBF

DON'T CARE

NULL

BIT B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7*

(MSB)

tCONV

*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY.

Hi-Z

LTC1096/98 F02

Figure 2. LTC1098(L) Operating Sequence Example: Differential Inputs (CH +, CH–)

Data Transfer

The CLK synchronizes the data transfer with each bit being

transmitted on the falling CLK edge and captured on the

rising CLK edge in both transmitting and receiving sys-

tems. The LTC1098(L) first receives input data and then

transmits back the A/D conversion result (half duplex).

Because of the half duplex operation, DIN and DOUT may be

tied together allowing transmission over just three wires:

CS, CLK and DATA (DIN/DOUT).

Data transfer is initiated by a falling chip select (CS) signal.

After CS falls the LTC1098(L) looks for a start bit. After the

start bit is received, the 3-bit input word is shifted into the

DIN input which configures the LTC1098(L) and starts the

conversion. After one null bit, the result of the conversion

CS

DIN 1

DIN 2

DOUT 1

DOUT 2

SHIFT MUX

ADDRESS IN

1 NULL BIT SHIFT A/D CONVERSION

RESULT OUT

LTC1096/98 • AI01

is output on the DOUT line. At the end of the data exchange

CS should be brought high. This resets the LTC1098(L) in

preparation for the next data exchange.

The LTC1096(L) does not require a configuration input

word and has no DIN pin. A falling CS initiates data transfer

as shown in the LTC1096(L) operating sequence. After CS

falls, the first CLK pulse enables DOUT. After one null bit,

14

Share Link: