LTC1096AI(RevB) View Datasheet(PDF) - Linear Technology

Part Name

Description

Manufacturer

LTC1096AI
(Rev.:RevB)

Micropower Sampling 8-Bit Serial I/O A/D Converters

Linear Technology 

LTC1096/LTC1096L

LTC1098/LTC1098L

APPLICATI S I FOR ATIO

cycle. Large external source resistors and capacitances

will slow the settling of the inputs. It is important that the

overall RC time constants be short enough to allow the

analog inputs to completely settle within the allowed time.

RC Input Filtering

It is possible to filter the inputs with an RC network as

shown in Figure 9. For large values of CF (e.g., 1µF), the

capacitive input switching currents are averaged into a net

DC current. Therefore, a filter should be chosen with a

small resistor and large capacitor to prevent DC drops

across the resistor. The magnitude of the DC current is

approximately IDC = 25pF(VIN/tCYC) and is roughly pro-

portional to VIN. When running at the minimum cycle time

of 29µs, the input current equals 4.3µA at VIN = 5V. In this

case, a filter resistor of 390Ω will cause 0.1LSB of full-

scale error. If a larger filter resistor must be used, errors

can be eliminated by increasing the cycle time.

RFILTER IDC

VIN

“+”

CFILTER

LTC1098

“–”

LTC1096/8 • F9

Figure 9. RC Input Filtering

Input Leakage Current

Input leakage currents can also create errors if the source

resistance gets too large. For instance, the maximum

input leakage specification of 1µA (at 125°C) flowing

through a source resistance of 3.9k will cause a voltage

drop of 3.9mV or 0.2LSB. This error will be much reduced

at lower temperatures because leakage drops rapidly (see

typical curve of Input Channel Leakage Current vs Tem-

perature).

REFERENCE INPUTS

The voltage on the reference input of the LTC1096 defines

the voltage span of the A/D converter. The reference input

transient capacitive switching currents due to the switched-

capacitor conversion technique (see Figure 10). During

each bit test of the conversion (every CLK cycle), a capaci-

tive current spike will be generated on the reference pin by

the ADC. These current spikes settle quickly and do not

cause a problem.

Using a slower CLK will allow more time for the reference

to settle. Even at the maximum CLK rate of 500kHz most

references and op amps can be made to settle within the

2µs bit time.

ROUT

REF+

5

LTC1096

EVERY CLK CYCLE

RON

VREF

GND

4

5pF TO 30pF

LTC1096/8 • F10

Figure 10. Reference Input Equivalent Circuit

Reduced Reference Operation

The minimum reference voltage of the LTC1098 is limited

to 3V because the VCC supply and reference are internally

tied together. However, the LTC1096 can operate with

reference voltages below 1V.

The effective resolution of the LTC1096 can be increased

by reducing the input span of the converter. The LTC1096

exhibits good linearity and gain over a wide range of

reference voltages (see typical curves of Linearity and Full

Scale Error vs Reference Voltage). However, care must be

taken when operating at low values of VREF because of the

reduced LSB step size and the resulting higher accuracy

requirement placed on the converter. The following fac-

tors must be considered when operating at low VREF

values.

1. Offset

2. Noise

3. Conversion speed (CLK frequency)

Offset with Reduced VREF

The offset of the LTC1096 has a larger effect on the output

code when the ADC is operated with reduced reference

voltage. The offset (which is typically a fixed voltage)

becomes a larger fraction of an LSB as the size of the LSB

is reduced. The typical curve of Unadjusted Offset Error vs

Reference Voltage shows how offset in LSBs is related to

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