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LTC1066-1CS View Datasheet(PDF) - Linear Technology

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LTC1066-1CS Datasheet PDF : 16 Pages
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LTC1066-1
TEST CIRCUIT
20
V
1µF
VIN
0.1µF
V+
0.1µF
ELLIPTIC
RESPONSE
V+
50:1
10k
LINEAR PHASE
RESPONSE
100:1
fCLK
(DUTY CYCLE
= 50% ±10%)
20k
1 OUT A
V+ 18
2 –IN A
OUT B 17
3 +IN A
+IN B 16
4 V
LTC1066-1 GND 15
5 V+
FILTERIN 14
6 CONNECT 1
13
COMP 2
7 FILTEROUT
8 50/100
CONNECT 2 12
COMP 1 11
9 CLK
V10
VOUT
20
V+
0.1µF
NOTE: RC COMPENSATION BETWEEN PINS 11 AND 13 IS
REQUIRED ONLY FOR CLOCK-TUNABLE OPERATION FOR:
50kHz < fCUTOFFs 100kHz.
15pF
THE TEST SPECIFICATIONS FOR:
fCLK = 2MHz, fCUTOFF = 40kHz, AND
fCLK = 4MHz, fCUTOFF = 80kHz
INCLUDE THE EFFECTS OF RC COMPENSATION.
30k
V
0.1µF
COMPENSATION DOES NOT INFLUECE THE SPECIFICATIONS
FOR:
fCLK = 400kHz, fCUTOFF = 8kHz.
FOR CLOCK-TUNABLE fCUTOFFs FROM 2kHz TO 50kHz
COMPENSATION IS NOT REQUIRED AND THE FILTER’S
PASSBAND PERFORMANCE IS REPRESENTED BY THE
TYPICAL SPECIFICATIONS AT:
fCLK = 400kHz, fCUTOFF = 8kHz.
1066-1 TC01
APPLICATIONS INFORMATION
DC PERFORMANCE
The DC performance of the LTC1066-1 is dictated by the
DC characteristics of the input precision op amp.
1. DC input voltages in the vicinity of the filter’s half of the
total power supply are processed with exactly 0dB (or
1V/V) of gain.
2. The typical DC input voltage ranges are equal to:
VIN = ±5.8V, VS = ±7.5V
VIN = ±3.6V, VS = ±5V
VIN = ±1.4V, VS = ±2.5V
With an input DC voltage range of VIN = ±5V, (VS =
±7.5V), the measured CMRR was 100dB. Figure 1
shows the DC gain linearity of the filter exceeding the
requirements of a 14-bit, 10V full scale system.
3. The filter output DC offset VOS(OUT) is measured with
the input grounded and with dual power supplies. The
VOS(OUT) is typically ±0.1mV and it is optimized for the
filter connection shown in the test circuit figure. The
filter output offset is equal to:
VOS(OUT) = VOS (op amp A) –IBIAS × RF = 0.1mV (Typ)
4. The VOS(OUT) temperature drift is typically 7µV/°C
(TA > 25°C), and – 7µV/°C (TA < 25°C).
5. The VOS(OUT) temperature drift can be improved by
using an input resistor RIN equal to the feedback resis-
75
VS = ±7.5V
50
TA = 25°C
fCLK = 1MHz
25
fC = 20kHz
0
–25
–50
–75
–100
–125
–6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6
INPUT VOLTAGE (VDC)
1066-1 F01
Figure 1. DC Gain Linearity
tor RF, however, the absolute value of VOS(OUT) will
increase. For instance, if a 20k resistor is added in series
with pin 3 (see Test Circuit), the output VOS drift will be
improved by 2µV/°C to 3µV/°C, however, the VOS(OUT)
may increase by 1mV(MAX).
6. The filter DC output offset voltage VOS(OUT) is indepen-
dent from the filter clock frequency (fCLK 250kHz).
Figures 2 and 3 show the VOS(OUT) variation for three
different power supplies and for clock frequencies up to
5MHz. Both figures were traced with the LTC1066-1
soldered into the PC board. Power supply decoupling is
very important, especially with ±7.5V supplies. If nec-
essary connect a small resistor (20) between pins 5
9

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