LTC1402CGN View Datasheet(PDF) - Linear Technology
Part Name
Description
Manufacturer
LTC1402CGN Datasheet PDF : 24 Pages
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LTC1402
APPLICATIONS INFORMATION
0
– 10
– 20
– 30
– 40
– 50
– 60
–70
0.1
1
10
100
FREQUENCY (MHz)
1000
1402 F07
Figure 7. CMRR vs Input Frequency
INPUT SPAN VERSUS REFERENCE VOLTAGE
The differential input range has a voltage span that equals
the difference between the voltage at the reference buffer
output VREF at Pin 5, and the voltage at the reference
ground AGND2 at Pin 6. The external reference voltage
may have any value between 2V and 5V. The internal ADC
is referenced to these two points. If you use an external
reference, tie the GAIN (Pin 7) to AVDD (Pin 1) to disable
the internal reference, and connect the external reference
between VREF (Pin 5) and AGND2 (Pin 6).
If you cut the reference voltage in half by halving the gain
of the reference buffer with the GAIN (Pin 7) tied to VREF
(Pin 5), the input span also cuts in half. In bipolar mode,
the differential input range changes from ±2.048V to
±1.024V, when the reference is cut in half. In unipolar
mode, the differential input range changes from 0V-
4.096V to 0V-2.048V, for the same reference cut in half.
Note that in both unipolar and bipolar modes, the input
range pivots around 0V with changing reference voltage.
AGND2 (Pin 6) has no direct effect on the ADC offset
voltage, it only affects input voltage span. Any external
offsetting voltages must be applied through the AIN+ and
AIN– inputs, as shown in Figure 10b.
SEVERAL LTC1402 ADCs MAY SHARE ONE
EXTERNAL REFERENCE
Figure 8 shows how several ADCs can share a single
common external reference. The VREF (Pin 5) and AGND2
(Pin 6) of several LTC1402 ADCs can be tied together to
share the same external reference in a data acquisition
system. Tie GAIN (Pin 7) to AVDD at each ADC to disable
all the internal references. When AGND2 (Pin 6) is tied to
the external ground plane, it sources 2.7mA ±30% typi-
cally; approximately 2mA are sourced through an internal
equivalent 2k resistance tied to the VREF (Pin 5) at 4.096V
and the remaining 0.7mA supply the internal reference
ground. The VREF (Pin 5) equivalent input resistance is the
same 2k tied to AGND2 (Pin 6). When you bus a common
reference voltage to several LTC1402 ADCs, you need to
keep PC board track resistance low to avoid reference
voltage attenuation at each ADC. For example, 0.5Ω of
track resistance to Pins 5 or 6 causes 0.025% of reference
voltage and input range reduction. Figure 8 shows op-
tional buffer amplifiers at each ADC to eliminate resistive
voltage drops from the common external reference to each
ADC. Figure 8 shows 10µF bypass capacitors tied to the
common analog ground plane, at VREF (Pin 5) and AGND2
(Pin 6), wired closely to each ADC to eliminate crosstalk of
internal ADC glitch currents from one ADC to another. The
10µF bypass capacitors are recommended whether you
drive Pins 5 and 6 with amplifiers, or with copper traces
4.096V
5V
10k
1k
0.1µF
LT1634AI-4.096
3
1/2 LT1368CS8 ANALOG
5V
INPUTS
2
6
–
8
7
5
+
5
10µF
1/2 LT1368CS8
2
6
–
1
3
+ 4 10µF
7
–5V
5V
AIN+
AIN–
LTC1402
VREF
AGND2
GAIN
•
•
•
3
1/2 LT1368CS8 ANALOG
5V
INPUTS
2
6
–
8
7
5
+
5
10µF
1/2 LT1368CS8
2–
1
6
3
+ 4 10µF
7
–5V
5V
AIN+
AIN–
LTC1402
VREF
AGND2
GAIN
1402 F08
Figure 8. Several LTC1402 ADCs Can Share a Single
External Reference
13
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