LTC2274I(RevB) View Datasheet(PDF) - Linear Technology

Part Name

Description

Manufacturer

LTC2274I
(Rev.:RevB)

16-Bit, 105Msps Serial Output ADC

Linear Technology 

LTC2274

APPLICATIONS INFORMATION

ANALOG INPUT

tAP

N

tCONV

N+1

N+2

ENC+

INTERNAL

PARALLEL DATA

N–6

tH

tL

N–5

N–4

N+8

N+3

N+9

N + 10

N+4

INTERNAL

8B/10B DATA

SERIAL DATA OUT

N–9

tBIT

N–8

N–7

LATP

N

N+1

N – 10

N–9

N–8

N–1

Figure 13. Timing Relationship of Analog Sample to Serial Data Out

N

2274 F13

Initial Frame Synchronization

In the absence of a frame clock, it is necessary to deter-

mine the start of each frame through a synchronization

process. To establish frame synchronization, Figures 14

and 15 illustrate the following sequence:

• The receiver issues a synchronization request via the

synchronization interface.

• If the synchronization request is active for more than

one ENC clock cycle, the LTC2274 will transmit a

synchronization preamble. When the ISMODE pin is

low the transmitted preamble will consist of consecu-

tive K28.5 comma symbols in conformance with the

JESD204 specification. When the ISMODE pin is high,

a series of idle ordered sets will be transmitted. The

idle ordered sets consist of a K28.5 comma followed by

either D5.6 or D16.2 as defined in IEEE Std 802.3-2002

part3, Clause 36.2.4.12.

• The receiver searches for the expected preamble and

waits for the correct reception of an adequate number

of preamble characters.

• The receiver deactivates the synchronization request.

• Upon detecting the deactivation of the synchroniza-

tion request, the LTC2274 continues to transmit the

synchronization preamble until the end of the frame.

• At the start of the next frame, the LTC2274 will begin

transmitting data characters.

• The receiver designates the first data character received

after the preamble transmission to be the start of the

frame. The first octet of the frame contains the most

significant byte of the ADC’s output word.

2274fb

24

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