LTC2274I(RevB) View Datasheet(PDF) - Linear Technology

Part Name

Description

Manufacturer

LTC2274I
(Rev.:RevB)

16-Bit, 105Msps Serial Output ADC

Linear Technology 

LTC2274

APPLICATIONS INFORMATION

START

SCRAMBLE ADC DATA

IF SCRAM IS ENABLED

GENERATE 8B/10B

CODE-GROUPS 1 AND 2

NO

IS FAM

ENABLED?

YES (FRAME ALIGNMENT MONITORING IS ENABLED)

TRANSMIT

CODE GROUP 1

TRANSMIT

CODE GROUP 1

TRANSMIT

CODE GROUP 2

NO

NO

IS SCRAM

YES (DATA SCRAMBLING IS ENABLED)

ENABLED?

IS CODE

GROUP 2 =

CODE GROUP 2

YES

OF LAST

FRAME?

IS CODE

NO

GROUP 2 =

YES

D28.7?

TRANSMIT

CODE GROUP 2

NO

WAS K28.7

TRANSMITTED

IN LAST

FRAME?

TRANSMIT

CODE GROUP 2

YES

TRANSMIT K28.7

AS CODE GROUP 2

TRANSMIT K28.7

AS CODE GROUP 2

TRANSMIT

CODE GROUP 2

2274 F18

END

Figure 18. Data Transmission Flow Diagram

PLL Operation

The PLL has been designed to accommodate a wide range

of sample rates. The SRR0 and SRR1 pins are used to

configure the PLL for the intended sample rate range.

Table 2 summarizes the sample clock ranges available

to the user.

Serial Test Patterns

To facilitate testing of the serial interface, three test patterns

are selectable via pins PAT0 and PAT1. The available test

patterns are described in Table 3. A K28.5 comma may be

used as a fourth test pattern by requesting synchronization

through the SYNC+/SYNC– pins.

Table 2. Sample Rate Ranges

SRR1

SRR0

0

x

1

0

1

1

SAMPLE RATE RANGE

20Msps < FS ≤ 35Msps

30Msps < FS ≤ 65Msps

60Msps < FS ≤ 105Msps

Table 3. Test Patterns

PAT1

PAT0

0

0

0

1

1

0

1

1

TEST PATTERNS

ADC Data

1010101010 Pattern

(8B/10B Code Group D21.5)

1+ x9 + x11 Pseudo Random Pattern

1+ x14 + x15 Pseudo Random Pattern

2274fb

30

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