LTC6909(RevA) View Datasheet(PDF) - Linear Technology
Part Name
Description
Manufacturer
LTC6909
(Rev.:RevA)
(Rev.:RevA)
Linear Technology
LTC6909 Datasheet PDF : 22 Pages
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LTC6909
Applications Information
peak electromagnetic radiation (or conduction) is reduced.
Output ripple may be somewhat increased, but its behavior
is very much like noise and its system impact is benign.
SUPPLY BYPASSING, SIGNAL CONNECTIons AND
PCB LAYOUT
Using the LTC6909 in spread spectrum mode naturally
eliminates any concerns for output frequency accuracy
and stability as it is continually hopping to new settings.
In fixed frequency applications however, some attention to
V+ supply voltage ripple is required to minimize additional
output frequency error. Ripple frequency components on
the supply line near the programmed output frequency of
the LTC6909 in excess of 30mVP-P could create an addi-
tional 0.2% of frequency error. In applications where a fixed
frequency LTC6909 output clock is used to synchronize
the same switching regulator that provides the V+ supply
to the oscillator, noticeable jitter of the clock may occur if
the ripple exceeds 30mVP-P .
The LTC6909’s accuracy is affected as described above
by supply ripple on the V+A pin only. The V+D pin is es-
sentially insensitive to supply ripple. The V+A pin supplies
the power for the analog section of the LTC6909 and its
current is largely constant for a given RSET resistor value.
The V+D pin supplies the digital section including the out-
put drivers and its current requirement consists mainly of
large bursts that digital circuitry requires when switching.
The peak current required by the output drivers is by far
the largest. The current is mainly dependent on output
capacitive loading and the supply voltage.
Figure 6 shows how to connect the V+A and V+D supply
pins to the power supply as well as a suggested PCB layout.
The PCB layout assumes a two layer board with a ground
plane in the layer beneath the part and 0805 sized passive
components. The PCB layout in Figure 6 is a guide and
need not be followed exactly. However, there are several
items to note from the layout as follows:
1. There should be a ground plane underneath and around
the part. Connect the GND pin to this plane through
multiple (three to four minimum) vias to minimize
inductance.
2. Place the bypass capacitors, C1 and C2, as close to the
V+A and V+D pins as possible to minimize the inductance
between the capacitor’s lead and the part’s pins.
3. The connection to the V+A and V+D pins to the main
supply should be through a low impedance path. If
the board has a V+ power plane, use it instead of the
top layer connection shown in Figure 6. Use multiple
vias (three to four minimum) at each point to connect
the V+A and V+D pins to the V+ plane to minimize the
inductance.
4. Connect the bypass capacitors, C1 and C2, directly to the
GND pin using a low inductance path. The connection
from C1 to the GND pin is easily done directly on the top
layer. The C2 path is more difficult but is accomplished
through multiple vias to the ground plane.
5. Connect the RSET resistor directly to the SET pin and
the V+A pin. Connecting the resistor to the V+ supply
through any manner other than directly to the V+A pin
will result greater frequency error.
6. Provide a ground shield around the RSET resistor and
its connections to V+A and SET. The SET pin is a fairly
high impedance point and is susceptible to interference
from noisy signal lines such as the part’s CMOS outputs
OUT1 through OUT8.
7. Route the output signals, OUT1 through OUT8, away from
the SET pin as soon as possible to minimize coupling.
8. When using the LTC6909 with spread spectrum disabled,
an active output is connected to the MOD pin. This is
best done by routing the OUT1 signal under the part
as shown in Figure 6. The ground shield between this
trace and the RSET resistor is very important to minimize
coupling of the OUT1 signal into the SET pin.
6909fa
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