M29W128GL60N6E View Datasheet(PDF) - Numonyx -> Micron

Part Name

Description

Manufacturer

M29W128GL60N6E

128 Mbit (16 Mb x 8 or 8 Mbx 16, page, uniform block) 3 V supply Flash memory

Numonyx -> Micron 

M29W128GH, M29W128GL

Command interface

6.2.2

to a 32-word/64-byte boundary. If the start address is not aligned to a 32-word/64-byte

boundary, the total programming time is doubled.

All the addresses used in the Write to Buffer Program operation must lie within the same

page.

To program the content of the write buffer, this command must be followed by a Write to

Buffer Program Confirm command.

If an address is written several times during a Write to Buffer Program operation, the

address/data counter will be decremented at each data load operation and the data will be

programmed to the last word loaded into the buffer.

Invalid address combinations or failing to follow the correct sequence of Bus Write cycles

will abort the Write to Buffer Program.

The Status Register bits DQ1, DQ5, DQ6, DQ7 can be used to monitor the device status

during a Write to Buffer Program operation.

It is possible to detect Program operation fails when changing programmed data from ‘0’ to

‘1’, that is when reprogramming data in a portion of memory already programmed. The

resulting data will be the logical OR between the previous value and the current value.

See Appendix D, Figure 28: Write to Buffer Program flowchart and pseudocode, for a

suggested flowchart on using the Write to Buffer Program command.

Enhanced Buffered Program command

The Enhanced Buffered Program command, available only in x 16 mode, makes use of the

device’s 256-word write buffer to speed up programming. 256 words can be loaded into the

write buffer. Each write buffer has the same A22-A8 addresses. The Enhanced Buffered

Program command dramatically reduces system programming time compared to both the

standard non-buffered Program command and the Write to Buffer command.

When issuing an Enhanced Buffered Program command, the VPP/WP pin can be either held

High, VIH, or raised to VPPH.

See Table 17: Program, Erase times and Program, Erase endurance cycles for details on

typical Enhanced Buffered Program times in both cases.

Three successive steps are required to issue the Enhanced Buffered Program command:

● The Enhanced Buffered Program command starts with two unlock cycles

● The third Bus Write cycle sets up the Enhanced Buffered Program command. The

setup code can be addressed to any location within the targeted block

● The fourth Bus Write cycle loads the first address and data to be programmed. There a

total of 256 address and data loading cycles.

To program the content of the write buffer, the Enhanced Buffered Program command must

be followed by an Enhanced Buffered Program Confirm command. The command ends with

an internal Enhanced Buffered Program Confirm cycle.

Note that address/data cycles must be loaded in an increasing address order (from

ADD[7:0]=00000000 to ADD[7:0]=11111111) and completely (all 256 words). Invalid

address combinations or failing to follow the correct sequence of Bus Write cycles will abort

the Enhanced Buffered Program.

The Status Register bits DQ1, DQ5, DQ6, and DQ7 can be used to monitor the device

status during an Enhanced Buffered Program operation.

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