M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB
Figure 9. Asynchronous Bus Read AC Waveforms
AA00-A-A1188
tAtAVVAAVV
VVAALLIDID
tAtAVVQQVV
tLtLLLEELL
LL
tEtELLQQXX
tEtELLQQVV
EE
ttGGttGGLLLLQQQQXVXV
G
G
tEtEHHLLXX
tAtAXXQQXX
ttEEttEEHHHHQQQQXZXZ
GD
GD
DQ0-DQ31
DQ0-DQ31
tGHQX
tGtGHHQQXZ
tGHQZ
OUTPUT
OUTPUT
See also Page Read
See also Page Read
AI04407C
AI0440 C
Table 16. Asynchronous Bus Read AC Characteristics.
Symbol
Parameter
Test Condition
M58BW016
80 90 100
Unit
tAVAV Address Valid to Address Valid
E = VIL, G = VIL Min
80
90 100
ns
tAVQV Address Valid to Output Valid
E = VIL, G = VIL Max
80
90 100
ns
tAXQX Address Transition to Output Transition
E = VIL, G = VIL Min
0
0
0
ns
tEHLX Chip Enable High to Latch Enable Transition
Min
0
0
0
ns
tEHQX Chip Enable High to Output Transition
G = VIL
Min
0
0
0
ns
tEHQZ Chip Enable High to Output Hi-Z
G = VIL
Max 20 20 20 ns
tELQV(1) Chip Enable Low to Output Valid
G = VIL
Max 80 90 100 ns
tELQX Chip Enable Low to Output Transition
G = VIL
Min
0
0
0
ns
tGHQX Output Enable High to Output Transition
E = VIL
Min
0
0
0
ns
tGHQZ Output Enable High to Output Hi-Z
E = VIL
Max 15 15 15 ns
tGLQV Output Enable Low to Output Valid
E = VIL
Max 25 25 25 ns
tGLQX Output Enable to Output Transition
E = VIL
Min
0
0
0
ns
tLLEL Latch Enable Low to Chip Enable Low
Min
0
0
0
ns
Note: 1. Output Enable G may be delayed up to tELQV - tGLQV after the falling edge of Chip Enable E without increasing tELQV.
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