M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB
Figure 16. Synchronous Burst Read - Continuous - Valid Data Ready Output
K
Output (1) V
V
R
V
tRLKH
V
V
(2)
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Note: Valid Data Ready = Valid Low during valid clock edge
1. V= Valid output.
2. R is an open drain output with an internal pull up resistor of 1MΩ. The internal timing of R follows DQ. An external resistor, typically
300kΩ. for a single memory on the R bus, should be used to give the data valid set up time required to recognize that valid data is
available on the next valid clock edge.
Figure 17. Synchronous Burst Read - Burst Address Advance
K
ADD
L
ADD
G
B
VALID
Q0
tGLQV
tBLKH
Q1
Q2
tBHKH
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